Impact of Fin Dimensions and Gate DielectricThickness on the Static Power Dissipation of 6T- FinFET SRAM Cell

The Triple gate FinFET architecture has emerged as a viable contender for the ultimate scalability of CMOS devices. FinFET structure offers better control over device leakage currents than the conventional bulk MOSFET structure. In this paper, we present the 6 transistor (6T) SRAM cell implementation using the 22 nm gate length FinFET devices modeled using a 3-D device simulator. The performance of an SRAM memory cell is judged by its static power consumption since the cell becomes active only during read or write operation. The static power dissipation of the 6T SRAM cell is analyzed using three variables: fin width, fin height and gate oxide thickness. Based on the simulation results, it is found that the fin width (Fw), fin height (Fh) and gate oxide thickness (Tox) are very important deciding factors on the leakage currents in the device. There is a phenomenal increase in short channel effects when the fin dimensions are increased. Also, the effects of Tox on the leakage currents in the devices are studied. The gate control on the channel can be accomplished with thinner fins at the expense of thicker gate oxides. From the simulation analysis, the static power dissipation of an SRAM cell can be reduced from 5.3 nW to 88 pW when moving from 1.0 nm Tox to 1.5 nm Tox for the same device provided that the fin is extremely thin. However short channel effects such as Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope of the devices increase by 19% and 1.4% respectively.